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| RF3163 0 Typical Applications * 3V CDMA/AMPS Cellular Handset * 3V CDMA2000/1XRTT Cellular Handset * 3V CDMA2000/1X-EV-DO US-Cellular Handset * Spread-Spectrum System Product Description 3.00 3V 900MHZ LINEAR POWER AMPLIFIER MODULE -A-B- The RF3163 is a high-power, high-efficiency linear amplifier module specifically designed for 3V handheld systems. The device is manufactured on an advanced third generation GaAs HBT process, and was designed for use as the final RF amplifier in 3V IS-95/CDMA 2000 1X/AMPS handheld digital cellular equipment, spreadspectrum systems, and other applications in the 824MHz to 849MHz band. The RF3163 has a digital control line for low power applications to lower quiescent current. The RF3163 is assembled in a 16-pin, 3mmx3mm, QFN package. 1.00 0.80 0.10 C 3.00 0.10 C 0.10 C 0.10 C Shaded areas represent pin 1. -C- 1.45 +0.10 -0.15 Dimensions in mm. SEATING PLANE SCALE: NONE 0.50 TYP. 1.45 +0.10 -0.15 0.10 C 0.08 C 0.05 0.00 0.30 TYP. 0.18 0.10 M C A B 0.50 TYP. 0.30 Optimum Technology Matching(R) Applied Si BJT Si Bi-CMOS InGaP/HBT GaAs HBT SiGe HBT GaN HEMT GaAs MESFET Si CMOS SiGe Bi-CMOS Package Style: QFN, 16-Pin, 3x3 Features * Input Internally Matched@50 * Output Internally Matched NC NC NC NC * 28dBm Linear Output Power * 41% Peak Linear Efficiency 12 RF OUT 11 VCC2 10 VCC2 9 VCC2 16 15 14 13 NC 1 VREG 2 VMODE 3 RF IN 4 Bias * -51dBc ACPR @ 885kHz * 55% AMPS Efficiency Ordering Information RF3163 RF3163 PCBA 3V 900MHz Linear Power Amplifier Module Fully Assembled Evaluation Board 5 VCC1 6 NC 7 NC 8 GND Functional Block Diagram RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com Rev A0 040730 2-689 RF3163 Absolute Maximum Ratings Parameter Supply Voltage (RF off) Supply Voltage (POUT 31dBm) Control Voltage (VREG) Input RF Power Mode Voltage (VMODE) Operating Temperature Storage Temperature Moisture Sensitivity Level (IPC/JEDEC J-STD-20) Rating +8.0 +5.2 +3.9 +10 +3.9 -30 to +110 -40 to +150 MSL 2 @ 260C Unit V V V dBm V C C Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Parameter High Power Mode (VMODE Low) Operating Frequency Range Linear Gain Second Harmonics Third Harmonics Maximum Linear Output Linear Efficiency Maximum ICC ACPR @ 885kHz ACPR @ 1.98MHz Input VSWR Stability in Band Stability out of Band Noise Power Specification Min. Typ. Max. Unit Condition T=25oC Ambient, VCC =3.4V, VREG =2.8V, VMODE =0V, and POUT =28dBm for all parameters (unless otherwise specified). 824 26.0 849 28.5 -35 -40 41 455 -51 -58 2:1 -30 -30 MHz dB dBc dBc % mA dBc dBc No oscillation>-70dBc No damage At 45MHz offset. T=25oC Ambient, VCC =3.4V, VREG =2.8V, VMODE =2.8V, and POUT =18dBm for all parameters (unless otherwise specified). 28 36 515 -46 -55 6:1 10:1 -133 dBm/Hz Low Power Mode (VMODE High) Operating Frequency Range Linear Gain Maximum Linear Output Maximum ICC ACPR @885kHz ACPR @1.98MHz Input VSWR Output VSWR Stability 824 21 18 849 24 125 -51 -61 2:1 MHz dB mA dBc dBc POUT =16dBm -46 -56 6:1 10:1 No oscillation>-70dBc No damage 2-690 Rev A0 040730 RF3163 Parameter FM Mode Operating Frequency Range AMPS Maximum Output Power AMPS Efficiency AMPS Gain AMPS Second Harmonics AMPS Third Harmonics 824 48 24 31 55 28 -35 -40 3.4 55 45 4.5 250 849 MHz dBm % dBc dBc V mA mA mA uA uS uS uA V V V V V High Gain Mode Low Gain Mode Specification Min. Typ. Max. Unit Condition T=25oC Ambient, VCC =3.4V, VREG =2.8V, VMODE =0V, and POUT =31dBm for all parameters (unless otherwise specified). -30 -30 4.2 80 70 5.5 6 40 5.0 0.5 2.95 3.0 0.5 2.8 Power Supply Supply Voltage High Gain Idle Current Low Gain Idle Current VREG Current VMODE Current RF Turn On/Off Time DC Turn On/Off Time Total Current (Power Down) VREG Low Voltage VREG High Voltage (Recommended) VREG High Voltage (Operational) VMODE Voltage 3.2 VMODE =low and VREG =2.8V VMODE =high and VREG =2.8V VMODE =high 0.2 0 2.75 2.7 0 2.0 2.8 Rev A0 040730 2-691 RF3163 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pkg Base Function NC VREG VMODE RF IN VCC1 NC NC GND VCC2 VCC2 VCC2 RF OUT NC NC NC NC GND Description No connection. Do not connect this pin to any external circuit. Regulated voltage supply for amplifier bias circuit. In power down mode, both VREG and VMODE need to be LOW (<0.5V). For nominal operation (High Power mode), VMODE is set LOW. When set HIGH, devices are biased lower to improve efficiency. RF input internally matched to 50. This input is internally AC-coupled. First stage collector supply. A 2200pF and 4.7F decoupling capacitor are required. No connection. Do not connect this pin to any external circuit. No connection. Do not connect this pin to any external circuit. Ground connection. Output stage collector supply. Please see the schematic for required external components. Same as pin 9. Same as pin 9. RF output. Internally AC-coupled. No connection. Do not connect this pin to any external circuit. No connection. Do not connect this pin to any external circuit. No connection. Do not connect this pin to any external circuit. No connection. Do not connect this pin to any external circuit. Ground connection. The backside of the package should be soldered to a top side ground pad which is connected to the ground plane with multiple vias. The pad should have a short thermal path to the ground plane. Interface Schematic 2-692 Rev A0 040730 RF3163 Evaluation Board Schematic 16 VREG C30 4.7 F VMODE C40 4.7 F J1 RF IN 3 4 50 strip 5 VCC1 C3 2200 pF P1 1 2 P1-3 3 4 P1-5 5 CON5 GND GND VCC1 GND VCC2 P2-5 P2-3 P2 1 2 3 4 5 CON5 GND GND VREG GND VMODE C20 4.7 F 6 7 8 10 9 C1 2200 pF C10 4.7 F C3 2200 pF 1 2 Bias 12 11 L* VCC2 15 14 13 50 strip J2 RF OUT * The current rating for the inductor needs to be 1A. One example is Toko 0603 multilayer inductor with the value of 1.8 nH (Toko part number LL1608-F1N8S). The value of the inductor can be from 1.5nH to 2.2nH. Different values of the inductor will give slight shift on the tradeoff between efficiency and ACPR. Rev A0 040730 2-693 RF3163 Electrostatic Discharge Sensitivity Human Body Model (HBM) Figure 3 shows the HBM ESD sensitivity level for each pin to ground. The ESD test is in compliance with JESD22-A114. >2000 V NC >2000 V NC 14 800 V NC 16 15 13 750 V NC >2000 V NC 1 2000 V VREG 2 2000 V VMODE 3 2000 V RF IN 4 12 750 V RF OUT 11 750 V VCC2 10 2000 V VCC2 9 2000 V VCC2 5 2000 V VCC1 6 2000 V NC 7 >2000 V NC >300 V NC 8 GND 13 250 V NC Figure 3. ESD Level - Human Body Model Machine Model (MM) Figure 4 shows the MM ESD sensitivity level for each pin to ground. The ESD test is in compliance with JESD22-A115. >300 V NC 250 V NC 16 15 14 >300 V NC 1 200 V VREG 2 200 V VMODE 3 200 V RF IN 4 12 250 V RF OUT 11 275 V VCC2 10 200 V VCC2 9 200 V VCC2 5 150 V VCC1 6 200 V NC 7 >300 V NC 8 GND Figure 4. ESD Level - Machine Model 2-694 Rev A0 040730 RF3163 PCB Design Requirements PCB Surface Finish The PCB surface finish used for RFMD's qualification process is electroless nickel, immersion gold. Typical thickness is 3inch to 8inch gold over 180inch nickel. PCB Land Pattern Recommendation PCB land patterns are based on IPC-SM-782 standards when possible. The pad pattern shown has been developed and tested for optimized assembly at RFMD; however, it may require some modifications to address company specific assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances. PCB Metal Land Pattern A = 0.64 x 0.28 (mm) Typ. B = 0.28 x 0.64 (mm) Typ. C = 0.64 x 1.28 (mm) D = 1.50 (mm) Sq. Dimensions in mm. 1.50 Typ. 0.50 Typ. Pin 16 B Pin 1 B B B Pin 12 A 0.50 Typ. A D A A 0.55 Typ. B 0.55 Typ. 0.75 Typ. B B B A 0.75 Typ. 1.00 Typ. C Pin 8 Figure 1. PCB Metal Land Pattern (Top View) Rev A0 040730 2-695 RF3163 PCB Solder Mask Pattern Liquid Photo-Imageable (LPI) solder mask is recommended. The solder mask footprint will match what is shown for the PCB metal land pattern with a 2mil to 3mil expansion to accommodate solder mask registration clearance around all pads. The center-grounding pad shall also have a solder mask clearance. Expansion of the pads to create solder mask clearance can be provided in the master data or requested from the PCB fabrication supplier. A = 0.74 x 0.38 (mm) Typ. B = 0.38 x 0.74 (mm) Typ. C = 1.60 (mm) Sq. Dimensions in mm. 1.50 Typ. 0.50 Typ. Pin 16 B Pin 1 B B B Pin 12 0.50 Typ. A A A A C A A A A B B B B Pin 8 0.75 1.50 Typ. 0.55 Typ. 0.55 Typ. 0.75 Figure 2. PCB Solder Mask Pattern (Top View) Thermal Pad and Via Design The PCB land pattern has been designed with a thermal pad that matches the die paddle size on the bottom of the device. Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern has been designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating routing strategies. The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size on a 0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results. 2-696 Rev A0 040730 |
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